Design Of Sample And Hold Circuit Using Op-Amp

Electrical Electronics Engineering

A Sample and Hold (S/H) circuit, integral in analog-to-digital conversion, maintains a constant output voltage level upon sampling an input signal, thus “holding” it steady until the next sampling cycle. Utilizing an operational amplifier (op-amp), the circuit comprises a sampling switch, a capacitor, and a buffer amplifier. During the sampling phase, the switch connects the input signal to the capacitor, charging it to the input voltage. Simultaneously, the op-amp’s negative feedback loop ensures the capacitor voltage mirrors the input voltage. As the switch opens for the hold phase, the capacitor retains the sampled voltage due to its high impedance, effectively isolating it from input fluctuations. The op-amp buffer prevents discharge by providing a high input impedance, maintaining a constant output voltage until the subsequent sampling cycle. This design optimizes for high input impedance, low leakage currents, and minimal settling time, ensuring accurate voltage retention and conversion.

ABSTRACT

This work is on an overview of sample and hold circuit using op-amp. As the name implies, a sample and hold circuit is a circuit which samples an input signal and holds onto its last sampled value until the input is sampled again. Sample and hold circuits are commonly used in analogue to digital converts, communication circuits, PWM circuits etc. The circuit shown below is of a sample and hold circuit based on uA 741 opamp, n-channel E SAMOSET BS170 and few passive components.

In the circuit MOSFET BS170 (Q1) works as a switch while opamp uA741 is wired as a voltage follower. The signal to be sampled (Vin) is applied to the drain of MOSFET while the sample and hold control voltage (Vs) is applied to the source of the MOSFET.

TABLE OF CONTENTS

COVER PAGE

TITLE PAGE

APPROVAL PAGE

DEDICATION

ACKNOWLEDGEMENT

ABSTRACT

CHAPTER ONE

INTRODUCTION

1.1 AIM OF THE STUDY

PURPOSE OF THE PROJECT
APPLICATION OF THE PROJECT
SIGNIFICANCE OF THE PROJECT
SCOPE OF THE PROJECT

CHAPTER TWO

LITERATURE REVIEW

OVERVIEW OF THE PROJECT
OPERATIONAL AMPLIFIER
HISTORICAL BACKGROUND OF AN OP-AMP
THE IC 741 OP-AMP CHARACTERISTICS
PIN DIAGRAM OF IC 741 OP-AMP
DESCRIPTION OF BS170 – MOSFET TRANSISTOR

CHAPTER THREE

SYSTEM DESIGN

BLOCK DIAGRAM SAMPLE AND HOLD CIRCUIT
SAMPLE AND HOLD OPERATION
SAMPLE AND HOLD CIRCUIT DIAGRAM
SAMPLE AND HOLD CIRCUIT WORKING

CHAPTER FOUR

TESTING AND RESULTS

SYSTEM SETUP PROCEDURES
COMPONENTS ASSEMBLING PROCEDURE
TESTING OF SYSTEM OPERATION
INSTALLATION OF THE COMPLETED DESIGN

CHAPTER FIVE

CONCLUSION
REFERENCES

CHAPTER ONE

1.0 INTRODUCTION

In electronics, a sample and hold circuit is an analog device that samples (captures, takes) the voltage of a continuously varying analog signal and holds (locks, freezes) its value at a constant level for a specified minimum period of time. Sample and hold circuits and related peak detectors are the elementary analog memory devices. They are typically used in analog-to-digital converters to eliminate variations in input signal that can corrupt the conversion process.^[2]

A typical sample and hold circuit stores electric charge in a capacitor and contains at least one switching device such as a FET (field effect transistor) switch and normally one operational amplifier.^[1] To sample the input signal the switch connects the capacitor to the output of a buffer amplifier. The buffer amplifier charges or discharges the capacitor so that the voltage across the capacitor is practically equal, or proportional to, input voltage. In hold mode the switch disconnects the capacitor from the buffer. The capacitor is invariably discharged by its own leakage currents and useful load currents, which makes the circuit inherently volatile, but the loss of voltage (voltage drop) within a specified hold time remains within an acceptable error margin.

1.2 AIM OF THE STUDY

The main objective of this work is to write on a circuit which samples an input signal and holds onto its last sampled value until the input is sampled again. Sample and hold circuits are commonly used in analogue to digital converts, communication circuits, PWM circuits etc. The circuit shown below is of a sample and hold circuit based on uA 741 opamp, n-channel E MOSFET BS170 and few passive components.

1.3 PURPOSE OF THE STUDY

Sample and hold circuits are used in linear systems. In some kinds of analog-to-digital converters, the input is compared to a voltage generated internally from a digital-to-analog converter (DAC). The circuit tries a series of values and stops converting once the voltages are equal, within some defined error margin. If the input value was permitted to change during this comparison process, the resulting conversion would be inaccurate and possibly unrelated to the true input value. Such successive approximation converters will often incorporate internal sample and hold circuitry. In addition, sample and hold circuits are often used when multiple samples need to be measured at the same time. Each value is sampled and held, using a common sample clock.

1.4 APPLICATION OF THE STUDY

The applications of sample and hold circuit include the following

Sampling Oscilloscopes
Data Distribution System
Digital Voltmeters
Analog Signal Processing
Signal Constructional Filters
Data Conversion System

1.5 SIGNIFICANCE OF THE STUDY

The function of the Sample and hold circuit is to sample an analog input signal and hold this value over a certain length of time for subsequent processing. Taking advantages of the excellent properties of MOS capacitors and switches, traditional switched capacitor techniques can be used to realize different S/H circuits.

With the help of sample and hold circuit we can take samples of the analogue signal, followed by a capacitor. It holds these sample for a particular period. As a consequence of this, a constant signal is generated this can be converted into the digital signal with the help of analogue to digital converters.

1.6 SCOPE OF THE STUDY

A typical circuit of the sample and hold stores electric charge in a capacitor and holds at least one switching device like a field effect transistor switch and usually one op-amp (operational amplifier).

To sample the i/p signal the switch unites the capacitor to the o/p of a buffer amplifier. This amplifier amplifies the capacitor so that the voltage across the capacitor is almost equal, or proportional to input voltage. In hold form, the switch separates the capacitor from the buffer. The capacitor is always discharged by its own outflow currents and helpful load currents, which makes the circuit essentially unstable, but the voltage drop in a particular hold time remains within a suitable error margin.