Design And Construction Of A False Triggering Eliminator For Timer 555

Electrical Electronics Engineering

The design and construction of a false triggering eliminator for the Timer 555 involves creating a circuitry system that effectively mitigates erroneous triggers, ensuring reliable operation. By integrating components such as capacitors, resistors, and diodes in strategic configurations, this device functions to stabilize the input signal, suppressing transient fluctuations that may lead to false triggers. The circuitry, tailored specifically for the Timer 555, enhances its accuracy and precision in timing applications, bolstering its performance and reliability. Through meticulous design and construction, this eliminator serves as an indispensable tool in various electronic systems, offering enhanced functionality and robustness in diverse applications.

ABSTRACT

Normally, false triggering of timer IC 555 takes place during power on, resulting in unwanted output, which starts the timer’s time cycle. The circuit becomes inefficient especially when the load has to be energised only when desired. This work is on a simple false triggering eliminator circuit for timer 555. The circuit is wired in monostable mode and grounded via N/O contact of RL(b) as well as switch S2. When power switch S1 is switched on, the circuit will not be grounded until switch S2 is momentarily pressed.

TABLE OF CONTENTS

TITLE PAGE

APPROVAL PAGE

DEDICATION

ACKNOWLEDGEMENT

ABSTRACT

TABLE OF CONTENT

CHAPTER ONE

1.0 INTRODUCTION

1.1      BACKGROUND OF THE PROJECT
1.2      AIM OF THE PROJECT
1.3      OBJECTIVE OF THE PROJECT
1.4      SIGNIFICANCE OF THE PROJECT
1.5      PURPOSE OF THE PROJECT
1.6      APPLICATION OF THE PROJECT
1.7      ADVANTAGES OF THE PROJECT
1.8      PROBLEM/LIMITATION OF THE PROJECT
1.9      PROJECT ORGANISATION

CHAPTER TWO

2.0 LITERATURE REVIEW

2.1 REVIEW OF RELATED STUDIES

2.2 REVIEW OF RELATED TERMS

CHAPTER THREE

3.0 CONSTRUCTION METHODOLOGY

3.1 SYSTEM CIRCUIT DIAGRAM

3.2 SYSTEM OPERATION

3.3 CIRCUIT DESCRIPTION

3.4 SYSTEM CIRCUIT DIAGRAM

3.5 CIRCUIT OPERATION

3.6 IMPORTANCE AND FUNCTION OF THE MAJOR COMPONENTS USED IN THIS CIRCUIT

3.7 POWER SUPPLY UNIT

CHAPTER FOUR

RESULT ANALYSIS

4.0 CONSTRUCTION PROCEDURE AND TESTING

4.1 CASING AND PACKAGING

4.2 ASSEMBLING OF SECTIONS

4.3 TESTING

4.4.1 PRE-IMPLEMENTATION TESTING

4.4.2 POST-IMPLEMENTATION TESTING

4.5 RESULT

4.6 COST ANALYSIS

4.7 PROBLEM ENCOUNTERED

CHAPTER FIVE

5.1 CONCLUSION

5.2 RECOMMENDATION

5.3 REFERENCES

False Triggering Eliminator Circuit

The circuit is wired in monostable mode and grounded via N/O contact of RL(b) as well as switch S2. When power switch S1 is switched on, the circuit will not be grounded until switch S2 is momentarily pressed. To provide the triggering pulse to the timer at pin 2, press switch S2 momentarily.

False Triggering Eliminator Circuit for Timer 555

To activate the relay for operating the load, switch on the power to the circuit by pressing switch S1 and then S2 momentarily. The resulting output at pin 3 goes high and energises relay RL to operate the load. Now after momentarily pressing S2, the circuit remains on as GND gets connected to N/O contact of RL(b). At the same time, pin 2 is disconnected from N/C contact of RL(b), which prevents further triggering.

The time period of relay energisation (approximately 3 minutes) can be easily changed by changing the values of resistor R1 and capacitor C1 according to the requirement to operate the load. At the end of the cycle, the relay gets de-energised and the circuit becomes ungrounded again.