High Level Synthesis Simulation ( A Research Study)

ACRONYMS

API Application Programming Interface.

ASI Accelera Systems Initiative.

AT Approximately-Timed.

CPU Central Processing Unit.

CUDA Compute Unified Device Architecture.

DES Discrete Event Simulation.

DMA Direct Memory Access.

FIFO First In, First Out.

FOFIFON Fast Ordered First In, First Out data exchaNge.

GPU Graphics Processing Unit.

GUI Graphical User Interface.

HDL Hardware Description Language.

HLS High Level Synthesis.

IDCT Inverse Discrete Cosine Transform

IMC Interface Method Call

IP Intellectual Property

IQZZ Inverse Quantization and Inverse Zig-Zag

ISS Instruction Set Simulator

KPN Kahn Process Network.

LT Loosely-Timed.

MPP Massively Parallel Processing.

MPSoC Multi-Processor System on Chip.

NoC Network on Chip.

OS Operating System.

OSCI Open SystemC Initiative.

PDES Parallel Discrete Event Simulation.

RGB Red, Green, Blue.

RTL Register Transfer Level.

SLDL System-Level Description Language.

SMP Symmetric Multi-Processing.

TLM Transaction Level Modeling.

YjC_BC_R  Luma and Blue/Red-differences Chroma.

ABSTRACT

FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we present an unbiased study of the high-level synthesis (HLS).

TABLE OF CONTENTS

COVER PAGE

TITLE PAGE

APPROVAL PAGE

DEDICATION

ACKNOWELDGEMENT

ACRONYMS

ABSTRACT

CHAPTER ONE

1.0      INTRODUCTION

1.1      BACKGROUND OF THE STUDY

• AIM OF THE STUDY
• SIGNIFICANCE OF THE STUDY
• PURPOSE OF THE STUDY
• LIMITATION OF THE STUDY
• APPLICATION OF THE STUDY

CHAPTER TWO

2.0      LITERATURE REVIEW

• HISTORICAL BACKGROUND OF THE STUDY
• SOURCE INPUT FOR HIGH-LEVEL SYNTHESIS
• REVIEW OF SYSTEM DESIGN STEPS
• COMPILATION AND MODELING OF THE SYSTEM
• REVIEW OF SEVERAL DESIGN FLOWS
• HIGH LEVEL SYNTHESIS TOOLS

CHAPTER THREE

3.0     CONSTRUCTION METHODOLOGY

3.1     INTRODUCTION

3.2      HARDWARE ACCELERATION BLOCKS

3.3    PRINCIPLE OF HIGH LEVEL SYNTHESIS

3.5    DESIGN FLOW

3.6    STUDIES AND EXPERIENCE ON HLS

3.7    INTERFACE OF A BLOCK DESIGNED WITH HLS

3.8    NECESSITY TO SPLIT DESIGNS IN SUB-BLOCKS

3.9    WRAPPING HLS CODE FOR TLM

3.10  PROBLEM STATEMENT

CHAPTER FOUR

• SIMULATION PROFILING
• EXISTING TOOLS
• A VISUALIZATION TOOL
• EVALUATION OF THE TRACE RECORDING OVERHEAD
• QUANTITATIVE VIEWS
• SIMULATION CHARTS

CHAPTER FIVE

• SUMMARY
• CONCLUSION
• REFERENCES

CHAPTER ONE

1.0                                                        INTRODUCTION

High-level synthesis (HLS), is described as an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior [1] Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages [2[, although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer level (RTL) design in a hardware description language (HDL), which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process [3].

Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation [4]. The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.

1.1                                           BACKGROUND OF THE STUDY

The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to move to higher abstraction levels. Raising the abstraction levels and accelerating automation of both the synthesis and the verification processes have for this reason always been key factors in the evolution of the design process, which in turn has allowed designers to explore the design space efficiently and rapidly.

In the software domain, for example, machine code (binary sequence) was once the only language that could be used to program a computer. In the 1950s, the concept of assembly language (and assem- bler) was introduced. Finally, high-level languages (HLLs) and associated compilation techniques were developed to improve software productivity. HLLs, which are platform independent, follow the rules of human language with a grammar, a syntax, and a semantics. They thus provide flexibility and portability by hiding details of the computer architecture. Assembly language is today used only in limited scenarios, primarily to optimize the critical parts of a program when there is an absolute need for speed and code compactness, or both. However, with the growing complexity of both modern system architectures and software applications, using HLLs and compilers clearly generates better overall results. No one today would even think of programming a complex software application solely by using an assembly language.

In the hardware domain, specification languages and design methodologies have evolved similarly.^1,2 For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simulation at the gate level appeared in the early 1970s, and cycle-based simulation became available by 1979. Techniques introduced during the 1980s included place-and- route, schematic circuit capture, formal verification, and static timing analysis. Hardware description languages (HDLs), such as Verilog (1986) and  VHDL (1987), have enabled wide adoption of simulation tools. These HDLs have also served as inputs to logic synthesis tools leading to the definition of their synthesizable subsets. During the 1990s, the first generation of commercial high-level synthesis (HLS) tools was avail- able commercially.^3,4 Around the same time, research interest on hardware-software codesign— including estimation, exploration, partitioning, interfacing, communication, synthesis, and cosimulation— gained mo- mentum.⁵ The concept of IP core and platform-based design started to emerge.^6-8 In the 2000s, there has been a shift to an electronic system-level (ESL) paradigm that facilitates exploration, synthesis, and verification of complex SoCs.⁹  This  includes  the  introduction of languages with system-level abstractions, such as SystemC, SpecC, or SystemVerilog, and the introduction of  transaction-level  modeling  (TLM). The ESL paradigm shift caused by the rise of system complexities, a multitude of components in a product (hundreds   of   processors   in   a   car,    for   instance), a multitude of versions of a chip (for better product dif- ferentiation), and an interdependency of component suppliers forced the market to focus on hardware and software productivity, dependability, interoperability, and reusability. In this context, processor customization and HLS have become necessary paths to efficient ESL design.¹⁰ The new HLS flows, in addition to reducing the time for creating the hardware, also help reduce the time to verify it as well as facilitate other flows such as power analysis.

1.2                                                     AIM OF THE STUDY

The main aim of this work is to discuss “High–level synthesis” as tools that raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements.

1.3                                           SIGNIFICANCE OF THE STUDY

High level synthesis (HLS) tools can provide significant benefits for implementing image processing algorithms on FPGAs. The higher level (usually C based) representation enables algorithms to be expressed more easily, significantly reducing development times. The higher level also makes design space exploration easier, making it easier to optimise the trade-off between resources and processing speed.

Raising the hardware design’s abstraction level is essential to evaluating system-level exploration for architectural decisions such as hardware and software design, synthesis and verification, memory organization, and power management. HLS also enables reuse of the same high-level specification, targeted to accommodate a wide range of design constraints and ASIC or FPGA technologies.

1.4                                                PURPOSE OF THE STUDY

The main purpose of this work is to make programming work easy with little time consumption.

1.5                                            LIMITATIONS OF THE STUDY

Unfortunately, it is not as simple as just compiling code for hardware. With most tools, the algorithm must be written in a particular style to enable the synthesis tools to identify and exploit parallelism [18]. This requires restructuring the code. Without such restructuring, the HLS tools can still derive a hardware realisation, but the resulting hardware can be bloated and suffer from poor performance [20].

The main limitation of using HLS is that it does not re-move the need for hardware design. If it is realised that the language is not software, but actually describing hardware, then it is possible to use the high level languages to also de-scribe relatively low level constructs where necessary.

1.6                                            APPLICATION OF THE STUDY

This study is used by programmers as tools to generate hardware implementations from algorithm descriptions in languages such as C/C++ and System C.